FIG. 1 illustrates a conventional control device 11 for controlling a semiconductor memory device 12. The semiconductor memory device 12 includes a memory cell array 122 and a sense amplifier circuit 121. The memory cell array 122 includes a plurality of bit lines (BL1-BLm, BLB1-BLBm) for transmitting data outputted by the memory cell array 122. The sense amplifier circuit 121 is coupled to the bit lines (BL1-BLm, BLB1-BLBm), and is operable between an enabled state and a disabled state. When operating in the enabled state, the sense amplifier circuit 121 senses the data outputted by the memory cell array 122 to generate a sensed output (vd). When operating in the disabled state, the sense amplifier circuit 121 does not perform sensing.
The conventional control device 11 includes a dummy memory cell group 111, an nMOSFET (N-type metal oxide semiconductor field effect transistor) 112, a pMOSFET (P-type metal oxide semiconductor field effect transistor) 116, an inverter 114, a signal generator 115 and a controller 113. The nMOSFET 112 has a first terminal that is coupled to the dummy memory cell group 111, a second terminal that is grounded, and a control terminal. The nMOSFET 112 cooperates with the dummy memory cell group 111 to form a tracking cell that emulates behavior of the memory cell array 122 when being read. The pMOSFET 116 has a first terminal that receives a pre-charge voltage (vp), a second terminal that is coupled to the first terminal of the nMOSFET 112, and a control terminal. The inverter 114 is coupled to the first terminal of the nMOSFET 112, has a switching threshold that is lower than the pre-charge voltage (vp), and generates a sense start signal based on a voltage (vb) at the first terminal of the nMOSFET 112. The signal generator 115 is coupled to the inverter 114 for receiving the sense start signal therefrom, is coupled further to the sense amplifier circuit 121 of the semiconductor memory device 12, and generates, based on the sense start signal and a predetermined time interval, a sense enable signal (vc) for controlling operation of the sense amplifier circuit 121 between the enabled state and the disabled state. The controller 113 is coupled to the inverter 114 for receiving the sense start signal therefrom, is coupled further to the control terminals of the MOSFETs 112, 116, and generates, based on the sense start signal, two control signals (TWL, TWL′) for respectively controlling the MOSFETs 112, 116.
Assuming that other than fabrication variations, all conditions the conventional control device 11 and the semiconductor memory device 12 are subjected to are controlled to be identical, FIG. 2 depicts voltages (VBL1, VBLB1) respectively at the bit lines (BL1, BLB1), the control signal (TWL) and the sense enable signal (vc) under a circumstance where the fabrication process varies to an nMOSFET-slow pMOSFET-slow (NSPS) corner, and FIG. 3 depicts the voltages (VBL1, VBLB1), the control signal (TWL) and the sense enable signal (vc) under a circumstance where the fabrication process varies to an nMOSFET-slow pMOSFET-fast (NSPF) corner.
Referring to FIGS. 1 to 3, initially, the memory cell array 122 is not read, and the control signals (TWL, TWL′) are both at a logic low level. Therefore, the voltages (VBL1, VBLB1) are both at a predetermined voltage value, then MOSFET 112 does not conduct, the pMOSFET 116 conducts, the voltage (vb) equals the pre-charge voltage (vp), the sense start signal and the sense enable signal (vc) are both at the logic low level, and the sense amplifier circuit 121 operates in the disabled state.
Thereafter, the memory cell array 122 is read, and the control signals (TWL, TWL′) both switch to a logic high level. As a consequence, one of the voltages (VBL1, VBLB1) (e.g., the voltage (VBLB1)) remains at the predetermined voltage value, the other of the voltages (VBL1, VBLB1) (e.g., the voltage (VBL1)) decreases gradually, the nMOSFET 112 switches into conduction, the pMOSFET 116 switches into non-conduction, and the voltage (vb) decreases gradually. When the voltage (vb) decreases below the switching threshold of the inverter 114, the sense start signal and the sense enable signal (vc) both switch to the logic high level, the sense amplifier circuit 121 enters the enabled state, and the control signals (TWL, TWL′) both switch to the logic low level. Therefore, the nMOSFET 112 switches into non-conduction, the pMOSFET 116 switches into conduction, and the voltage (vb) increases gradually. The sense start signal switches to the logic low level when the voltage (vb) increases above the switching threshold of the inverter 114. The sense enable signal (vc) remains at the logic high level and the sense amplifier circuit 121 remains in the enabled state for the predetermined time interval before the sense enable signal (vc) switches to the logic low level, making the sense amplifier circuit 121 enter the disabled state.
In the aforesaid case, the switching threshold of the inverter 114 in the circumstance where the fabrication process varies to the NSPF corner is higher than that in the circumstance where the fabrication process varies to the NSPS corner. Therefore, a time point (t1) (at which the sense enable signal (vc) switches to the logic high level in the circumstance where the fabrication process varies to the NSPF corner as shown in FIG. 3) is earlier than a time point (t2) (at which the sense enable signal (vc) switches to the logic high level in the circumstance where the fabrication process varies to the NSPS corner as shown in FIG. 2) with respect to a time point (t0) (at which the control signal (TWL) switches to the logic high level as shown in FIGS. 2 and 3), and a difference (V2) between the voltages (VBL1, VBLB1) at the time point (t1) as shown in FIG. 3 is less than that (V1) at the time point (t2) as shown in FIG. 2.
In a first case where the conventional control device 11 is designed such that the difference (V1) at the time point (t2) equals a minimum voltage difference which the sense amplifier circuit 121 can sense correctly, the semiconductor memory device 12 can have a relatively high operation speed. However, although the sense amplifier circuit 121 can correctly sense the difference (V1) at the time point (t2) in the circumstance where the fabrication process varies to the NSPS corner, it cannot correctly sense the difference (V2) at the time point (t1) in the circumstance where the fabrication process varies to the NSPF corner.
In a second case where the conventional control device 11 is designed such that the difference (V2) at the time point (t1) equals the minimum voltage difference (i.e., the time point (t1) in the second case is concurrent with the time point (t2) in the first case with respect to the time point (t0)), the sense amplifier circuit 121 can not only correctly sense the difference (V1) at the time point (t2) in the circumstance where the fabrication process varies to the NSPS corner, but also correctly sense the difference (V2) at the time point (t1) in the circumstance where the fabrication process varies to the NSPF corner. However, the operation speed of the semiconductor memory device 12 is relatively low in the second case since the time point (t2) in the second case is later than that in the first case with respect to the time point (t0).